Introducing IMFT's 3D NAND
Introducing IMFT's 3D NAND
In the past 2D or 'planar' NAND was laid down in layers. Each layer was one cell 'high' which consists of the actual storage substrate and a 'bottom' controller substrate. In the case of MLC NAND this meant each layer was 2-bits of data high, and with TLC it is 3bits of data high - and how many rows of cells wide the die package was. Since making the actual footprint of the chip larger wasnít efficient, manufacturers had only two options when increasing densities: utilize a finer-grain manufacturing process or stack these two dimensional layers upon each other to increase the overall density of each NAND IC.
Both of these solutions arenít without their own potential challenges and switching up the manufacturing process was -at best- a stopgap measure. Every node shrink made the NAND transistors more fragile, and each layer added made cooling the NAND cells more and more difficult. As such combining the two has long been considered a dead-end design route that was quickly becoming harder and harder to improve upon.
3D NAND on the other hand is not laid down in separate layers like carpet, and rather is built upon a three dimensional cube-like structure. How each NAND manufacturer goes about the actual design differs, but IMFT does things in a very interesting way. Instead of opting for a radical new manufacturing process they have taken the best parts of planar NAND and applied it to their first generation 3D NAND design. The end result is 3D NAND that looks somewhat like an apartment building.
Much like an apartment building, there are individual cells laid out in a grid pattern throughout the chipís length and width as well as above and below. To command and control each cell there are hallways (horizontal pathways) and elevators (vertical pathways) built in between the cells that connect not only the cells but also join up to the CMOS control circuits.
These pathways not only allow for command and control but also enhance cooling so that the cells packed in at the chipís center of the chip donít have heat limitations like they would in a 2D NAND chip of such massive heights. To further help keep temperatures in check this 'apartment' has a metal 'roof' with integrated cooling fins. This built-in cooling feature does actually decrease the density per 'floorí. However, any capacity reduction is a minor concern since instead of including a main controller substrate at each floor of this 32 story high-rise apartment building (that would be required in 32 layer planar NAND die package) Micron has only needed to include one at the base of the 'building'.
In theory there really is no limit to how high this building-type structure can get, but 32 seems to be the point where things get tricky from both a latency and heat standpoint. As such we fully expect 'higher' IMFT 3D NAND chips to require either a new underlying design or new engineering feats before being ready for primetime.
Limiting to only 32 layers for this first generation does however represent a very nice increase in data densities. When combined with TLC (rather than MLC) storage transistors, a single 3D NAND 'layer' can theoretically pack in 384Gbits of data Ė or 48 Gigabytes. For reference purposes, remember that IMFT's planar NAND maxed out at 128Gbit, though once again that was MLC and not TLC.
To further boost total capacity per 'chip' 3D NAND has another ace up its sleeve in the form of layering. As with 2D planar NAND Crucial has been able to just use two layers of 3D NAND per package to create the necessary 96GB die package required for the MX300 LE 750GB. It is this combination of 3D design with layering that will allow future Crucial solid state drives to hit multi-Terabyte levels without requiring a massive PCB or complicated controller. This will be of special interest to M.2 enthusiasts as the lack of room for more than four NAND die packages ('ICs') on a M.2 2280's PCB was one the main bottlenecks to that form-factor's acceptance with mainstream consumers.
In the meantime, 750GB drives may not sound like such a massive leap over the densest planar NAND designs, but reliability and performance are paramount with this new generation rather than just increased data densities. To help alleviate reliability concerns IMFT hasnít radically changed the underlying NAND transistor storage technology like Samsung has. Instead of opting for the technically superior Charge Trap design they have carried over the proven Floating Gate transistor of previous planar designs. This not only makes manufacturing less costly with more consistent output, but it also removes one more variable from the equation when coding the controller firmware.
As an added bonus it also grants the firmware team the luxury of carrying over many of their previous works to this new generation without too much tweaking. This means Drive Write Acceleration, wear-leveling algorithms, and the like do not have to be radically altered just because the underlying NAND layout has been changed. As time passes more tweaking will obviously occur, but even launch day firmware will be fairly adept at handling the new NAND. It also means that tracking down issues and fixing them is a much more straightforward affair without the learning curve associated with a major transistor change Ė that may or may not perform in exactly the same manner as floating gates do.
This is why when a rather large performance bug was discovered late in the product testing cycle it only pushed the MX300ís release back from early Q2 to late Q2 release. In this short time span Crucial not only diagnosed and fixed the issue but also had the luxury of a full quality control / quality assurance testing cycle before launching this series series. Compare and contrast that with when TLC first came out and the issues that plagued Samsung's Evo line (that were never entirely fixed in the Evo 840) and there is a lot to be said for taking the conservative approach when transitioning from Floating Gate to Trap Charge transistor storage.
Regardless of opinions on which is the more optimal approach, there is no denying the fact that even though Crucial has not only gone from tried and true MLC to TLC but also from 2D to 3D NAND, that they have been able to keep the durability of the NAND extremely high. This increased durability is of course mainly due to Drive Write Acceleration and its ability to 'transform' TLC into quasi-SLC NAND but does point to toward the 3D NAND being not as fragile as what usually accompanies a new generation of NAND.
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