FX-8350 CPU Review; AMD's Vishera Arrives

Author: SKYMTL
Date: October 22, 2012
Product Name: FX-3850
Part Number: FD8350FRHKBOX
Warranty: 3 Years
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Revising Bulldozer; Say Hello to Piledriver & Vishera

The entire raison d’ętre behind Vishera is to provide the next logical step in the Bulldozer architecture’s ongoing maturation process. This time around, an Enhanced Bulldozer design has been implemented in order to create the Piledriver cores found within these new CPUs.

Piledriver doesn’t represent a brand new core design for AMD. Rather, it is an evolutionary step that aims to implement the gradual changes without the costs associated with ramping up a brand new architecture. As such, we can’t expect miracles but Piledriver should bring some noteworthy benefits to the table for the new FX-series.

Based around a 32nm manufacturing process, equipped with a pair of cores and up to 2MB of L2 cache, the basic Bulldozer module hasn’t changed all that much in its Piledriver guise. There have been some minor changes like the addition of the FMA3 and F16C instruction sets but AMD’s major focus here was to increase the instruction per clock (IPC) rate and generally improve upon the operational frequencies of the previous generation. The relative maturity of GlobalFoundries’ 32nm node also led to a substantial leakage reduction when compared against Bulldozer.

Diving a bit further into the Piledriver, the enhancements seem to be everywhere. Most are supposed to home in on streamlining branch scheduling throughout the architecture and optimize certain elements for quicker communication.

However, there have been some sacrifices here since –as with the previous Bulldozer design- space has been given over for the aforementioned new instruction sets rather than retain a strict adherence to legacy standards. As a result, programmers using compilers like Visual Studio 2008 and older versions of Visual Basic could see their applications run slower on Bulldozer-based cores due to a lack of x87 and other optimizations.

While this may not be an optimal solution for every situation an emphasis upon SSE, AVX, XOP and other new, emerging instruction sets has allowed AMD to maximize their die space for current (and future) computing needs. Plus, the number of programs that use the legacy instruction sets is diminishing at a rapid rate.

AMD has also put some focus into single thread performance, which was a major stumbling point for the original Bulldozer design. Improvements have been instituted but AMD admits their architecture is still less than optimal for these situations.

The internal workings of Vishera processors are arranged in a similar way to Zambezi, with the only major difference being the replacement of typical Bulldozer cores with the updated Piledriver version. As with the previous generation, the top-end eight core Vishera chips are split into four distinct modules. Each of these modules consists of two x86 processing cores, a set of shared L1 cache and 2MB of L2 cache. This design can be scaled from the high end FX-8350’s eight cores and 8MB of L2 cache downwards to lower end processors like the quad core FX-4300 with its 4MB of cache.

Meanwhile, the unified L3 cache is shared between all of the modules, thus creating an adaptable pipeline between processing stages which can be dynamically assigned depending on how many cores are engaged.

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