AMD Trinity A10-5800K APU Review

Author: SKYMTL
Date: October 9, 2012
Product Name: AMD A10-5800K
Part Number: AD580KWOHJBOX
Warranty: 3 Years
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Revising Bulldozer; Say Hello to Piledriver

Instead of sticking to the old Athlon / Husky CPU architecture that graced the Llano APUs, AMD's Trinity has now moved on towards higher performance CPU cores that are based off of a revision of the modular Bulldozer design. Code named Piledriver (otherwise known as Enhanced Bulldozer), we’ll be seeing this optimized design in dedicated eight core Vishera FX-branded CPUs sometime in the very near future.

Naturally, the inclusion of Piledriver CPU cores should make a difference in terms processing performance over the previous generation but there are some tertiary benefits as well. Turbo Core 3.0 has been incorporated, resulting in better efficiency through highly adaptable clock speed scaling and instruction paths have been optimized as well.

Based around a 32nm manufacturing process, equipped with a pair of cores and up to 2MB of L2 cache, the basic Bulldozer module hasn’t changed all that much in its Piledriver guise. There have been some minor changes like the addition of the FMA3 and F16C instruction sets but AMD’s major focus here was to increase the instruction per clock (IPC) rate and generally improve upon the operational frequencies of the previous generation. The relative maturity of GlobalFoundries’ 32nm node also led to a substantial leakage reduction when compared against Bulldozer.

For those of you keeping track of such things, there’s a huge difference between Llano’s Propus / Husky core architecture and this one. We won’t bore you with fine grain details here (more about the Bulldozer architecture can be found HERE) but the move to Piledriver compute modules has resulted in an impressive performance increase for the Virgo platform over Llano.

Diving a bit further into the Piledriver, the enhancements seem to be everywhere. Most are supposed to home in on streamlining branch scheduling throughout the architecture and optimize certain elements for quicker communication.

However, there have been some sacrifices here since –as with the previous Bulldozer design- space has been given over for the aforementioned newer instruction sets rather than a strict adherence to legacy standards. As a result, programmers using compilers like Visual Studio 2008 and older versions of Visual Basic will see their applications possibly run slower on Bulldozer-based cores due to a lack of x87 and other optimizations. While this may not be an optimal solution for every situation this emphasis upon SSE, AVX, XOP and other new, emerging instruction sets has allowed AMD to maximize their die space for current (and future) computing needs. Plus, the number of programs that use the legacy instruction sets is diminishing at a rapid rate.

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