Diving into Intel's X79 Express Chipset
Diving into Intel's X79 Express Chipset
With Intel’s Sandy Bridge platform well integrated into certain areas of the market, we have seen an expanding number of motherboard chipsets which support it. Originally, B65, H61, H65 and P67 motherboards were released with or soon after the initial launch while the recent introduction of Z68 “Cougar Point” brought RST SSD caching into the mix. What we haven’t seen up to this point is an enthusiast level X-series chipset made available but the new Sandy Bridge E platform is about to change that.
Called the X79 (code named Patsburg), this chipset is the spiritual successor to the long lasting Tylersburg X58 and finally ushers the PCH era into the high end market. With Bloomfield finally on its way out, X79-based motherboards should be the go to products on Intel’s high end platform for the foreseeable future. Will still be around when the Panther Point platform is introduced in 2012 for Ivy Bridge CPUs and will be compatible with any Socket 2011 processors from now until the launch of Haswell in 2013. This is one of the reasons why Intel decided to go with the 7x moniker instead of sticking with Sandy Bridge’s 6x naming scheme.
Some of you may remember the last X-series chipset –the X58- from our original Nehalem review. Back then a 3-chip solution consisting of a processor, MCH and ICH was used but Intel has gradually moved towards a simplified approach by grouping functions into two areas: on the CPU die and within a so called Platform Controller Hub or PCH. This centralization leads to higher performance and increased platform efficiency.
The basic functionality built into the Socket 2011 processors closely mirrors that of previous Sandy Bridge chips but the capabilities have been expanded to better suit enthusiasts. An Integrated Memory Controller acts as a backbone for up to four high speed DDR3 memory channels, each rated at 12.8 GB/s while a separate controller takes care of the PCI-E lanes.
Speaking of PCI-E lanes, Sandy Bridge E processors support a serious number of lanes; 40 to be exact. These can be configured in a variety of different layouts depending on the number of slots Intel’s motherboard partners implement on their boards. We are told every X79 motherboard will include at least two 16x PCI-E 3.0 slots for a full speed 16x / 16x Crossfire or SLI, a vast improvement over the 8x / 8x supported by P67 and Z68. There is also the option of having a third or fourth graphics slot (running at 8x bandwidth) for triple and quad GPU setups.
The X79 Express Chipset incorporates the motherboard’s I/O functions and its features closely mirror those of the P67 and Z68. It includes support for up to 14 USB 2.0 and two SATA 6Gb/s ports while also including the usual Intel HD Audio module. Many will be disappointed with the omission of integrated USB 3.0 and Thunderbolt support but it seems like Intel isn’t ready to plunge into those waters just yet. Nonetheless, there is an additional 8 PCI-E 2.0 lanes that can be used for more slots or add on-controllers so boards can include USB 3.0 and other non natively supported features.
We should also mention that Patsburg-based motherboards won’t support Smart Response Technology or SSD caching at this point.
Connecting the processor to the PCH is a second generation Direct Media Interface along with an optional SCSI Controller Unit. However, the Intel FDI (Flexible Display Interface) from P and Z-series boards has been removed since none of the SB-E processors will come with onboard graphics controllers.
The Direct Media Interface (DMI) hasn’t changed either. When necessary, it can function with the same peak bandwidth as four PCI-E 2.0 lanes or 5 GT/s (20Gb/s) but most of the time it will be operating at lower speeds ensure optimal efficiency.
One thing that we didn’t see on previous chipsets is the SCU Uplink which Sandy Bridge E processors are capable of providing. In essence this link allows for a dedicated path between the PCH and processor in order to speed up storage performance and decrease latency. The only downside to using the SCU function is its need for a portion of the CPU’s PCI-E lanes (in this case four) which in essence limits the secondary PCI-E function to a 4x link down from 8x and eliminates the possibility for native 3-way GPU compatibility.
Unfortunately, there is a bit of confusion here since some of Intel’s documentation (including the diagram above) lists the Sandy Bridge processor as having 40 PCI-E 2.0 lanes while most of their other pieces list full compatibility with the upcoming PCI-E 3.0. This is a bit of a slippery slope but after digging much further with Intel and their motherboard vendors, a clearer picture is beginning to emerge.
According to our conversations these new processors do indeed have PCI-E 3.0 compatibility built in –at least one paper- but they haven’t been officially certified by the PCI-SIG. The main reason for this lack of the necessary certification is a lack of compatible add-in cards from AMD and NVIDIA to test on the dedicated graphics lanes. So while SB-E is physically capable of providing up to 40 PCI-E 3.0 lanes, we likely won’t see anyone make a big deal about it until some additional testing can be done in the near future.
With that being said, some motherboard partners feel strongly enough about the upcoming certification for the SB-E chips that they will be including PCI-E 3.0 stickers on their X79 boards’ packaging and marketing materials. We will even see a few instances of PCI-E 2.0 / 3.0 switching options included within the BIOS.
Intel themselves are quite confident as well as they say: “The processor features up to 40 lanes of PCI Express 3.0 links capable of 8.0 GT/s…”
With all of this additional bandwidth coming their way, graphics card manufacturers are feeling quite confident as well. According to NVIDIA they have seen a substantial increase in overall 3-Way SLI performance when using the native solution on X79 instead of the usual 16x / 16x + NF200 setup some X58 boards used. Remember, this is based off of the exact same dX79Sabertoothrs being used in each instance and comparable processors so it looks like higher end SLI configurations could finally see better scaling.
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