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  #81 (permalink)  
Old February 1, 2011, 03:34 PM
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Quote:
Originally Posted by AkG View Post
. The ONLY way to be 100% sure is use the 3rd party Sata 6gb/s controller's ports. The downside to this is...anyone using SSDs will lose TRIM abilities as those 3rd party controller cant pass on the commands. :(

this bring me a question, I build a SB for a friend the other day, an Asus P8P67 with 4 sata 3gb/s and 2 sata 6gb/s on the Intel chipset and 2 others 6 gb/s on an marvell controller.

SO the 6gbs on Intel controler and are they passing the trim command ?
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  #82 (permalink)  
Old February 1, 2011, 03:35 PM
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I am not doubting Sky, but some credible sources have said otherwise. While 5-6% might not seem too much to worry about, it is still something I would like to rule out of any system I am troubleshooting.

I didn't think about trim issue either by using the marvell controller. Good point.
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  #83 (permalink)  
Old February 1, 2011, 03:41 PM
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There is a reason the SATA 3 ports connected to the chipset are backwards compatible in my opinion: SATA 2 functionality still gets routed through the same routes as the standard ports. Otherwise they would have had to double up on functionality while still trying to reduce the size of the PCH in order to save power and money while increasing the number of chips per wafer. Why add complication when I/O calls for ALL SATA 2 devices can be taken care of by the same "sections" of the die?

I am not saying this is 100% correct since I am not an engineer. What I am saying is that it just doesn't make sense to me how SATA 2 devices operating on PCB-controlled SATA 3 ports would NOT be affected by this.

Also, every other retailer, editor and *cough* blogger I have seen talking about this has basically rephrased what Intel talked about in their conference call without really taking a step back to analyse what they're saying. The mass of op-ed and "analysis" pieces have been done quickly, in a blind rush to generate traffic rather than try to replicate the issue. "Let's take Intel's word for it" has been the mantra it seems.

We have begun the process of reaching out to Intel's team and the engineering teams of motherboard vendors to see if we can duplicate their results. I have a number of boards sitting here right now running non-stop I/O tests on SATA 2 and SATA 3 ports so we will see what happens...
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Old February 1, 2011, 03:46 PM
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Originally Posted by SKYMTL View Post
We have begun the process of reaching out to Intel's team and the engineering teams of motherboard vendors to see if we can duplicate their results. I have a number of boards sitting here right now running non-stop I/O tests on SATA 2 and SATA 3 ports so we will see what happens...
This is good to see and hear. Its not just retailers, but sites such as Anandtech that that say the problem does not affect ports 0 and 1, and makes no mention that it has to be SATA 3 port and SATA 3 drive to avoid the issue. So the assumption really is widespread. Intel (on a blog, if this is the source of your blog comment) also says Anand's analysis is a good explanation in the comments section:
Technology@Intel · Chipset With Potential Problem - What To Do
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Old February 1, 2011, 03:48 PM
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so you guys are saying that if i use the one port to wipe me drives 24/7 one should start seeeing issues soon?

been using the same board,well setup, some dude was supposed to pick up but cant atm to wipe hdds, and its been going on a couple

weeks straight. now wiping drives probably doesnt do much, but still mr dod and guttman should generate some traffic on

them buses i reckon.
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  #86 (permalink)  
Old February 1, 2011, 03:54 PM
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Had a conversation with Intel a few minutes ago. Here is the deal:

The SATA 2 and SATA 3 logic cores on the PCH are separate. When the SATA 3 logic detects a SATA 2 device, it runs in compatibility mode WITHOUT switching back to the SATA 2 logic.

This means the SATA 3 transistors when running in SATA 2 mode is COMPLETELY SEPARATE from any issues.



The reason I assumed this is because other controllers like Marvell default legacy commands through the standard SATA 2 channels. If Intel had done this, then ALL ports would have been affected.

So....I stand corrected. Happily I might add.
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Old February 1, 2011, 04:07 PM
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Quote:
Originally Posted by botat29 View Post
this bring me a question, I build a SB for a friend the other day, an Asus P8P67 with 4 sata 3gb/s and 2 sata 6gb/s on the Intel chipset and 2 others 6 gb/s on an marvell controller.

SO the 6gbs on Intel controler and are they passing the trim command ?
Yup. Intel controllers are one of the VERY few controllers which can pass the TRIM command (assuming all other TRIM requirements are met). :)
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  #88 (permalink)  
Old February 1, 2011, 04:56 PM
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what to think about that?

From TECHREPORT:

Quote:
6-series SATA bug traced to single transistor
by Geoff Gasior — 10:51 AM on February 1, 2011
Additional details have emerged on Intel's 6-series chipset flaw. AnandTech has learned that the problem was traced back to a single transistor in the PLL clocking tree for the 3Gbps SATA controller. Anand explains:
The aforementioned transistor has a very thin gate oxide, which allows you to turn it on with a very low voltage. Unfortunately in this case Intel biased the transistor with too high of a voltage, resulting in higher than expected leakage current. Depending on the physical characteristics of the transistor the leakage current here can increase over time which can ultimately result in this failure on the 3Gbps ports. The fact that the 3Gbps and 6Gbps circuits have their own independent clocking trees is what ensures that this problem is limited to only ports 2 - 5 off the controller.
The kicker is that this transistor isn't even needed for the chipset to function correctly. At least that makes the solution a simple one. The new 6-series chipset stepping will have the transistor in question disabled.
What? just that? Disable the defective transistor in the next P67 chip stepping and tell the customer this WASN'T NEEDED,so no loss?

C'MON
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  #89 (permalink)  
Old February 1, 2011, 05:07 PM
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Quote:
Originally Posted by Delavan View Post
what to think about that?

What? just that? Disable the defective transistor in the next P67 chip stepping and tell the customer this WASN'T NEEDED,so no loss?

C'MON
Even better, engineering samples were completely unaffected by this, so there was no way any review sites could find out anything unless they went out and collected retail samples. Some bone headed engineer put that transistor there without even thinking and used it as the retail stepping.
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Old February 1, 2011, 05:16 PM
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Originally Posted by ilya View Post
Even better, engineering samples were completely unaffected by this, so there was no way any review sites could find out anything unless they went out and collected retail samples. Some bone headed engineer put that transistor there without even thinking and used it as the retail stepping.
Oh boy! I bet this will take a bite out of his salary
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