A Closer Look at BiCS Technology
A Closer Look at BiCS Technology
Toshiba has been working on their BiCS technology since 2007. In the intervening years they have further refined and evolved the basic idea of vertically stacking NAND. Back in 2007 it was indeed a groundbreaking idea but since then others have successfully done it. What Toshiba has done however is to think outside the box and create TLC NAND that is arguably superior to all others.
There are numerous ways in which this BiCS 3 NAND is arguably superior to the IMFT 3D NAND we have previously looked at. The first is in exactly how the NAND is designed and how it is programmed. In a
floating gate (FG) NAND cell, like IMFT's 3D NAND, this 'floating' gate is the conductor of electricity. So to change the voltage in a cell the gate itself provides the pathway. In a Charge Floating Trap (CFT) NAND the gate is an insulator that simply impedes the flow of current.
This may not sound like much of a difference, as both are Negative-AND logic gates, but it really is significant. In standard floating gate designs high write loads cause stress on the crystal lattice of the gate and eventually tiny fractures start appear in the lattice. Over time these fractures or 'oxide defects' build up and allow electrons to flow freely into and out of the cell regardless of the gate's state. This causes a short circuit in the cell, rendering it unable to hold a charge. In laymen's terms these fractures are what 'kill' a NAND cell. The smaller the fabrication process the smaller the gate, the more severe the impact even small fractures can have. This is why historically every new smaller fabrication node size came with a reduction in cell life. It is also a large part of why IMFT's first gen '3D' NAND was not built on a smaller node process than the proceeding '2D' NAND process, and may never go smaller - or as Micron states on their 3D NAND page (https://www.micron.com/products/nand-flash/3d-nand) "This vertical approach lets us expand the size of each 3D NAND cellthe lithography is actually larger than our latest planar NAND."
Even more concerning is this issue becomes much more acute when dealing with NAND cells which hold 3 bits or 6 voltage states and 'bit-flipping' (or more accurately an error in the voltage of the cell) can readily happen after only a small portion of the gate is damaged from use. This is why TLC was always considered by enthusiasts to be the red-headed step child of the industry.
Conversely a Charge Floating Trap does not suffer from this issue until a relatively large portion of the gate is damaged. This is because these small fractures only create a short circuit at the electron level and drain off only the electrons that are 'touching' the fracture. Leaving the rest of the electrons in the cell to control the voltage adequately enough that the controller can still accurately tell what the cell state is. In laymen's terms CFT is more durable than floating gate and requires a lot less handholding or 'housekeeping' by the controller, freeing up valuable cycles for more important things such as real-time IO requests.
Equally important these fractures in the gate are also a lot less likely to occur in the first place. CFT gate's do not use the same erase technique that is needed with floating gates to ensure a cell is wiped clean of residual charge. Instead it can use a gentler, lower voltage, but faster process that still ensures the cell is completely clean and ready for new data storage.
To imagine this difference, take two scenarios. In one scenario you have a water balloon filled with water. In the other you have the same latex balloon but it is covering a glass of water that is tipped upside down. For these scenarios the latex balloon is the gate and the water represents the electrons in a cell. In both scenarios you are going to randomly prick the balloon with a very sharp, very small needle. This needle represents the random damage that happens to a NAND cell's gate when being heavily used, or simply being erased. The end result will be that while the balloon over the glass will indeed loose water over time it will only be 'dripping' out of the holes. Whereas the balloon filled with water is going to catastrophically fail after only a few pin pricks. That is the difference between FG and CFT gates, albeit exaggerated for effect.
Floating Gate manufactures are well aware of this issue and have done their best to mitigate the damage done during erases by simply using less voltage but for a longer period of time. This makes for a slower erase cycle and one that is still more damaging than its Charge Floating Trap counterpart. Barring going back to 50nm process nodes there is only so much manufactures can do with floating gate designs to increase longevity. Even then it is a tradeoff between early cell death or higher levels of performance. Toshiba were simply the first to see these issues associated with ever decreasing node size, and were willing to spend money on coming up with a solution.
This major difference between typical floating gate and charge floating trap design is indeed significant but it is not the only reason CFT is seen by many experts as the more elegant solution. Another reason is that, while it still is a possibility, the chance of capacitive coupling occurring is greatly reduced compared to floating gate designs. Capacitive coupling happens when these 'oxide defects' do not drain the cell voltage enough for the controller to notice, and mark the cell as dead, but enough that these free electrons bleed over to adjacent cells. When enough of this bleed over happens the gates themselves become linked as there is now a pathway connecting them together that is not monitored by the controller.
In simplistic terms, capacitive coupling means that when the controller initiates a cell charge state change in the any one of these coupled cells, the voltages of all the cells can randomly change. This in turn can change a 0 into a 1 in not just one bit but up to three bits per linked cell. Which in turn leads to read errors in these damaged cells, and in turn requiring the controller to implement its ECC to try and recover the data. The net result is not only a risk of loss of data but performance also suffers. In an effort to reduce this issue floating gate NAND based drives shuffle and rewrite the data on a very short schedule usually measured in weeks - so as to reduce this issue from becoming serious, as well as to uncover these misbehaving cells early. It does however reduce NAND life as the long term cumulative effect of all this writing, erasing, and re-writing creates the very issue it is trying to solve.
These are the main reasons that Toshiba was the first NAND manufacturer to start thinking about a new way of creating NAND that did not suffer from these issues. It is why they were also the first to start expending significant resources on research and development of CFT based NAND storage (circa 2007). Even though Samsung was the first to the marketplace with a CFT design, via Samsung's 'V-NAND' technology, Toshiba's greater experience should translate into fewer real-world issues. Put another way, the chances of the early generation Samsung Evo issues happening to Toshiba and their BiCS NAND is a lot less.
Further helping cement Toshiba's take on CFT as arguably the superior option to both Samsung's V-NAND and IMFT's 3D NAND is the fact that Toshiba has not taken a linear path to their NAND cell layout. As we detailed in our Crucial MX300 review IMFT 3D NAND, much like Samsung V-NAND, is laid out like a large apartment building with vertical and horizontal interconnects ('elevators' and 'hallways') with the NAND cells themselves in 'apartments' in between these controller routes.
In BiCS these vertical and horizontal paths are not separate and distinct. Instead each vertical pathway is U shaped with vertical lines of NAND interconnected at the 'base of the building'. Amongst other things, this in theory should allow for faster inter-IC transfer of data from one 'apartment' block to another for example during internal housecleaning when a NAND block needs to be refreshed or erased. What is not theory is that BiCS TLC NAND is significantly faster than IMFT or Samsung TLC NAND when it comes to erase cycles.
With other NAND manufacture's '3D' NAND, the controller can only initiate an erasure at the single page (IMFT) or two page (Samsung) level. With BiCS the controller can flash three pages per erase cycle. This is important as all 3D NAND -including BiCS relies upon a pseudo-SLC write buffer to achieve acceptable write performance. This buffer may vary in size from manufacture to manufacture but once this group of TLC cells acting in SLC mode is exhausted the controller has to rely upon the rest of the TLC NAND. Until the pseudo-SLC buffer can be flushed of data, erased, and made ready for new incoming write requests performance does drop precipitously. TLC NAND is not only rather slow to complete write requests compared to SLC and MLC, but the controller has to dedicate some of its cycles to internal transfer of data from SLC to TLC NAND, other cycles to handling incoming write requests, and others still to erasing the SLC write buffer. That is a lot more demand than the controller can supply when only able to erase one or two pages per cycle. As such TLC BiCS based drives should be able to get out of this 'emergency mode' faster than their counterparts.
The reason that CFT based NAND storage are not as common as their FG counterparts all boils down to cost of manufacture. Floating gate storage is a very mature process with most of the major bugs worked out, or at the least negated as best as possible. CFT gates on the other hand may date back to the 60s, but creating a NAND design process that scale up to industrial levels has proven difficult. It is not a simple process like FG and has taken Toshiba many, many years to perfect. A perfect example of this is the Toshiba OCZ TR200 series may be the first mass consumer drive released to the general public with BiCS but this is not to say it uses first generation BiCS NAND. Instead it is third generation (aka 'BiCS 3'). Compare and contrast this ultra conservative approach of not releasing a product before it is fully baked with Samsung who simply want 'First to market!' accolades with consumers paying the price and Toshiba certainly appears to have the better, more mature technology. As they should as they were the ones who invented the idea of using a Charge Trap for NAND based storage in the first place.
Taken as a whole Toshiba's fresh take on NAND design is extremely exciting and may help breathe life into a technology that some like IMFT and their 3DXpoint phase change memory technology believe is quickly becoming irrelevant and antiquated. It remains to be seen if this newer approach can indeed stave off the almost inevitable change-over from NAND to newer 'solid state' technologies.
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