AMD Trinity: Going Mobile with a New APU

Author: SKYMTL
Date: May 14, 2012
Product Name: AMD Trinity APU
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Revising Bulldozer; Say Hello to Piledriver

Some of you may be wonder what a Piledriver (the artist formerly known as Enhanced Bulldozer) section is doing in an APU review but there’s a reason behind our…errr…AMD’s madness. Instead of sticking to the old Athlon / Husky CPU architecture that graced the Llano APUs, AMD has now moved on towards higher performance CPU cores that are based off of a revision of the modular Bulldozer design. Code named Piledriver, we’ll be seeing this optimized design in dedicated eight core CPUs sometime in the future but for the time being, it has been included in Trinity.

Naturally, the inclusion of Piledriver CPU cores should make a night and day difference in terms of x86 performance over the previous generation but there are some tertiary benefits as well. Turbo Core 3.0 has been incorporated, resulting in better efficiency through highly adaptable clock speed scaling and instruction paths have been optimized.

Based around a 32nm manufacturing process, equipped with a pair of cores and up to 2MB of L2 cache, the basic Bulldozer module hasn’t changed all that much in its Piledriver guise. There have been some minor changes like the addition of the FMA3 and F16C instruction sets but AMD’s major focus here was to increase the instruction per clock (IPC) rate and generally improve upon the operational frequencies of the previous generation. The relative maturity of GlobalFoundries’ 32nm node also led to a substantial leakage reduction when compared against Bulldozer.

For those of you keeping track of such things, there’s a huge difference between Llano’s Propus / Husky core architecture and this one. We won’t bore you with fine grain details here (more about the Bulldozer architecture can be found HERE) but the move to Piledriver compute modules has resulted in a claimed 29% performance increase for the mobile platform.

Diving a bit further into the Piledriver, the enhancements seem to be everywhere. Most are supposed to home in on streamlining branch scheduling throughout the architecture and optimize certain elements for quicker communication. We’ll cover more of this when Piledriver launches on the desktop so for the time being, jump to the next page to see how this change in core module design affects the Trinity APUs.

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