Tick+ The Ivy Bridge Microarchitecture & Process
Tick+ Ivy Bridge Microarchitecture & Process
As mentioned in the introduction, Intel’s development schedule called a ‘Tick’ in 2012, which is generally just a process shrink of the previous microarchitecture, but thankfully Intel haven't been resting on their laurels. At IDF 2011, Intel referred to Ivy Bridge as a Tick+ due to the significant enhancements in the graphics and media portion of the chip, as well as the numerous little new architectural features, microarchitectural improvements, and power savings.
Having said that, the highlight of Ivy Bridge is obviously the new cutting-edge 22nm manufacturing process, and the revolutionary 3-D or Tri-Gate transistor technology that got a lot of publicity a few months ago. In development since first announced in 2002, the characteristics of tri-gate transistors is that they utilize a fin-based, multi-gate transistor design. Instead of a having a flat two-dimensional stream like on 2D planar transistors, the conducting channel is wrapped in three-dimensional fins. This allows for control of the current on all three sides of the fin, instead of just on one side. The end result is a significant reduction in leakage and power consumption, while simultaneously allowing for much higher switching speeds. If you want an visual explanation in layman’s terms, Intel has a neat little video with Mark T. Bohr, a Senior Fellow and Director of the Manufacturing Group.
The end result of all that advanced manufacturing technology is obviously the Ivy Bridge die itself. As mentioned of the previous page, by transitioning to the new 22nm manufacturing processor, Intel has managed to increase the transistor count from 1.16 billion on Sandy Bridge up to 1.4 billion Ivy Bridge, while simultaneously shrinking the die size has from 216mm2 down to 160mm2.
While the bulk of additional transistors are due to the larger and more powerful IGP, there are a number of other small changes as well.
As usual, Intel have been relatively secretive with respect to what tweaks they have done to the cores. However, while we do know that most elements of Ivy Bridge have remained the same as on Sandy Bridge, but they have cleaned up the design a bit to further improve single threaded performance. The floating point unit was given some attention and now throughout was doubled, which is an improvement that should reveal itself in computationally demanding workloads.
Graphics aside, the new parts come in the form of enhancements to security, power management, and memory support. The security enhancements are the addition of Digital Random Number Generator (DRNG) and Supervisory Mode Execute Protection (SMEP). These are hardware-level protection mechanisms that give us a glimpse into what Intel's plans are now that it owns McAfee.
The power management improvements are numerous, but the only one really stands out. Although most areas of the processor can now be power gated, Intel addressed the one area that wasn't, the DDR3 memory interface. Although not a large source of current leak, the DDR3 interface can now be totally shutdown if there's no memory activity.
The memory controller remains basically unchanged, but it does now natively support DDR3-1600 as the default. In dual-channel form that means up to 25.6GB/s of memory bandwidth, up from 21.3GB/s on Sandy Bridge. The maximum supported DDR3 frequency has also increased, from DDR3-2133 on Sandy Bridge to DDR3-2800. Intel have also tweaked the multipliers, so memory frequency can be increased in smaller 200MHz steps (instead of just 266MHz). Although more relevant for the mobile sector, support for 1.35V DDR3L has been added in order to further help reduce system power consumption.
In order to improve overclocking, have implemented real-time multiplier adjustments, thereby eliminating the need to reboot when increasing/decreasing multipliers from within the OS. More importantly they have also increased the CPU multiplier limits from 57X to 63X. This should help alleviate one of the significant overclocking bottlenecks that was discovered on Sandy Bridge.
The integrated PCI-E controller has obviously been updated. It now supports PCI-E 3.0 while also featuring 20 channels. Regrettably, only 16 are enabled on the consumer desktop side. You will need a workstation-class C200 series chipset and Xeon processor to get access to the full 20 lanes. Nevertheless, this new interface operates at 8.0 GT/s, and with 1GB/s of bandwidth per lane, allows for up 32GB/s of aggregate bandwidth to one PCI-E x16 slot.
The new IGP is clearly a huge part of Ivy Bridge, both literally and figuratively. The HD Graphics 4000 takes up almost half the die on the Core i7-3770K. This new top-end IGP has 16 Execution Units (EUs) and a maximum frequency of 1.15GHz. Now that might not sound like much of an improvement when compared to the previous HD Graphics Card 3000 ( 12 EUs – up to 1.35GHz), but these new EU's are about twice as powerful as their predecessors, and altogether Intel is claiming an up to 60% increase in GPU performance. To ensure an optimal gaming experience, Intel have also added compatibility with DirectX 11, OpenCL 1.1, OpenGL 3.1, and support for three display outputs. To cap it all off Intel has further improved the performance of their unmatched hardware video encoding/decoding Quick Sync Video technology, and improved media CODEC support and image quality.
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