The Tahiti Pro Core Uncovered
The Tahiti Pro Core Uncovered
Once we bring together the items we have seen on the last few pages, a clearer picture of the Tahiti core begins to emerge. From a high level standpoint there are quite a few similarities between the outgoing and incoming core layouts but the functionality introduced by the Graphics Core Next architecture makes this a whole new ballgame.
Letís start with the basic Graphics Core Next design elements since that is where most of the advances lie. The ďcoreĒ of the fully enabled Tahiti core houses 32 Compute Units broken up into two engines of 16CUs each. If you remember our previous discussions, each one of those CUs houses four SIMDs with 64 cores and four texture units for a total of 2048 Stream Processors and 128 TMUs in a fully enabled Tahiti XT core. When this ~500 SP and 32 TMU increase over Cayman is combined with GCNís new Compute Unit processing features, AMD claims a 40% increase in compute and texture fillrate performance from one generation to the next.
The Tahiti Pro meanwhile uses all of the same elements as its big brother but has four Compute Units disabled. The result is a 1792 core, 112 TMU part that still retains an identical number of ROPs, tessellators, cache and memory controllers as the Tahiti XT so performance shouldnít take a massive hit in every application.
While the main core elements have changed drastically, items like the Geometry Engines and render backends havenít seen much in the way of architectural changes and some may even think they have been overlooked. There are still eight combined Render Output Units which hold four ROPs each, giving the Tahiti core a maximum of 32 ROPs, or exactly the same number as Cayman. Granted, the shared L2 cache and additional memory bandwidth does help these attain an approximate 5% real world increase in pixel fillrate but thatís not much considering the improvements apparent elsewhere.
The Geometry Engines house the most critical parts of any DX11 architecture and while it looks like AMD hasnít done much here, we canít forget that Cayman already incorporated several key advances in DX11 processing. Nonetheless, there have been some fancy moves going on behind the scenes with the two tessellators being upgraded, increasing their theoretical throughput.
Moving down to the ďlowerĒ part of the Tahiti block diagram we come to the L2 cache and memory controllers, both of which have seen a fundamental evolution away from previous designs. Instead of being incorporated into four distinct blocks and being tied to the Render Backends, the full amount L2 cache is now shared throughout the core and scales independently from the ROPs and memory controllers. It has also been doubled in size to 768KB, ensuring there is enough for storing information on the fly.
The GDDR5 memory controllers donít feature any behavioral differences from the ones found on Cayman but two additional 64-bit units have been added to make a 384-bit interface which powers up to a dozen modules. As we already mentioned, they have been decoupled from the rest of the architecture so in theory we could see a 384-bit card with less ROPs than the fully endowed version of Tahiti.
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