Intel Sandy Bridge-E Core i7-3960X CPU Review

Author: MAC
Date: November 14, 2011
Product Name: i7 3960X
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Expanding the Tock - Inside the SB-E Architecture

As we have explained in the past, Intel’s development cycle operates on their tick/tock strategy. The "tick" is a shrinking of the previous microarchitecture’s manufacturing process (45nm --> 32nm) and the "tock" is a new microarchitecture. In order to continue pushing CPU technology forward, Intel’s strives to achieve a tick and tock cycle at least every 2 years. Between these two stages, Intel has gotten very good at releasing a number of reworked and enhanced models, which is what we are seeing today with Sandy Bridge-E (SB-E), a high-end desktop variant of the existing Sandy Bridge microarchitecture with a few noteworthy tweaks.

8 cores/16 threads - 20MB L3 Cache – 2.27 Billion Transistors - 435mm2

As mentioned in the intro, for years it was believed that SB-E would be introduced as an eight-core part, but regrettably due to power concerns consumer-oriented models are limited to six cores. As you can see on die shot above, the two extra cores and 5MB of extra L3 cache are still there, but they have been disabled and hopefully power-gated. There will be eight-core Xeon offerings, but those parts will be lower clocked in order to stay within the 130W TDP limit, and thus generally be slower in most consumer-oriented software.

Now although the SB-E die might look drastically different than the mainstream quad-core die, the parts are merely re-arranged, enlarged (IMC/L3 Cache/PCIE), or stripped out entirely (ie: the IGP). It is the great advantage of the modular block design philosophy that Intel's first unveiled with Nehalem.

The fundamentals are the same though, 3 ALUs (arithmetic logic unit) and 3 AGUs (address generation units) per core, two 256-bit AVX-capable FPUs (floating-point units) per core, 32KB of L1 data cache + 32KB L1 instruction cache per core, and 256KB of L2 cache per core. However, L3 cache has been bumped up to 2.5MB per core, and the associativity of that cache has been greatly enhanced from 16-way to 20-way ensuring low latency and much higher bandwidth. The extremely high bandwidth 256-bit ring bus interconnect still links all the pieces of the die together.

Obviously, the Uncore/System Agent has received the greatest overhaul. The new integrated memory controller (IMC) supports four independent 64-bit memory channels with 1 unbuffered DIMM per channel. This quad-channel IMC also now natively supports DDR3-1600, a nice bump over the previous DDR3-1333 ceiling. Combined these changes have created a memory sub-system that is theoretically capable of 51.2GB/s of bandwidth.

Now the biggest unknown with this launch was whether these chips would actually support PCI-Express 3.0 or not. The answer to that question is regrettably not quite as simple as we would like. While Sandy Bridge-E’s new and improved integrated PCI-E controller supports up to 40 PCI-E 2.0 lanes, PCI-E 3.0 support is still on the fence. The capability is absolutely there, however compatibility simply has not yet been tested thoroughly enough for Intel’s to give it a thumbs up. Once PCI-E 3.0 devices start trickling into Intel’s labs for QA and testing, then we are convinced that they will publicly announced support. Feel free to check out the chipset section for additional info about PCI-E 3.0 on the LGA2011 platform.

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