Tessellation Done Right?
Tessellation Done Right?
We all know that tessellation can be used by a developer to add a large amount of high detail geometry to a scene, but in the past this meant a hefty performance penalty for AMD’s DX11 cards. Without the ability to significantly change the way in which the architecture processes tessellation, AMD needed a way to decrease the overall “cost” of implementing one of the integral features of the DX11 ecosystem.
In the previous pages we mentioned that AMD has augmented tessellation performance on the Northern Island family of graphics cards and to do so they basically increased the efficiency at which tessellated scenes are processed.
AMD claims the current way of implementing tessellation is wasteful. According to a paper published at SIGGRAPH 2010 (PDF), the excessive use of tessellation can lead to sub-optimal rasterizer utilization and increasing the triangle mesh size to include up to 16 pixels wouldn’t decrease image quality but would vastly increase tessellation efficiency.
In addition to the under utilization of a GPU’s rasterizers, the issues with low pixel to triangle ratios have been far reaching. Due to the massive number of polygon edges, implementing MSAA algorithms can cause a staggering performance hit which runs counter to DX11’s claims of streamlining the rendering process. Developers have also run into problems with over-shadowing which again causes a performance hit and also reduces the overall realism of a given scene.
As the triangle size increases to encompass more pixels, the overall number of shader passes per pixel decreases as well but there is a trade off in terms of overall image quality and detail. In order to overcome this, developers have to strike a balance between shader / tessellation performance and overall mesh fidelity.
It is important to remember that these advances cannot be made at the hardware level; developers have to begin using the methods necessary to increase tessellation performance across a wide cross section of hardware. In these slides, AMD is only showing what is possible if developers use methods for higher tessellation efficiency in their upcoming titles.
While most developers have yet to begin utilizing different tessellation methods, AMD is moving forward with their own efficiency improvements for the Northern Islands architecture. This involves using some of the ideas we outlined above but transporting them to the hardware level instead of waiting for developers to play catch up.
Achieving higher tessellation efficiency for the HD 6000 series involves a number of hardware tweaks along with pushing a method called adaptive tessellation. Adaptive tessellation involves applying higher levels of tessellation to objects that are closer to the camera while objects further away will be rendered using lower levels. Using this type of method could also decrease the performance impact of applying certain anti aliasing algorithms to tessellated scenes.
Does this translate into higher performance in comparison to the HD 5000-series? Yes, but only at lower tessellation levels. However, once the tessellation factor increases beyond a certain point, the overall tessellation performance of AMD’s HD 6000 series levels off and is only slightly above a HD 5800 series card.
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