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  #31 (permalink)  
Old November 4, 2008, 09:15 AM
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Ok yeah whatever..ah huh.. um... ok ... ^^

Yeah the writing was worded so well.. But the testing is the real thing, FixT.. I salute you too.. Great job.

Well SKY says he has more in store for us, well I can't wait now..
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  #32 (permalink)  
Old November 4, 2008, 09:21 AM
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Quote:
Originally Posted by Tazer-[X] View Post
HT has always been a bomb, theres a reason why it doesnt work, never has. Its disrupting a superpipelined CPU to reload data and instructions.
Nehalem does 4 instructions at a time in parallel. New architecture. Never has does not mean never will, look at the results.
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  #33 (permalink)  
Old November 4, 2008, 09:29 AM
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umm, NO. When I talk of DEC alpha, it was one die that executed 4 instructions per clock cycle. NOw we have the same technology in teh POWER series. Those are multi core. The intel is doing 1 inctruction per clock cycle, but with 4 cores.
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  #34 (permalink)  
Old November 4, 2008, 09:51 AM
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Great job MAC, well researched and complete, looking forward to the future articles.
Future looks bright for Intel with this one. wow.
It would be interesting if high-resolution gaming improves because of the separation
of the chipset and the memory controller. With the fsb the northbridge had to handle
memory and PCIe, now they will be separate.
PCIe should have all the bandwidth it needs and more now.

Supreme commander can be a real memory hog once you get hundreds of units going, glad you started including it.
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  #35 (permalink)  
Old November 4, 2008, 10:24 AM
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Quote:
Originally Posted by Tazer-[X] View Post
umm, NO. When I talk of DEC alpha, it was one die that executed 4 instructions per clock cycle. NOw we have the same technology in teh POWER series. Those are multi core. The intel is doing 1 inctruction per clock cycle, but with 4 cores.
4 simultaneous instructions per core. Straight from the mouth of intel.
http://www.intel.com/pressroom/archi...er_nehalem.pdf
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  #36 (permalink)  
Old November 4, 2008, 10:32 AM
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Great review, well done. Lest OC !
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  #37 (permalink)  
Old November 4, 2008, 11:07 AM
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Great review guys. Some constructive criticism.

+
- Very thorough testing, research, explanations and conclusions.
- Great photos, gifs, etc.
- Great selection of comparison CPUs.
- 5 runs/bench...OMG! What a workload.
- Great writing style.
_

- Proof-reading. I know... you guys were "under the gun".
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  #38 (permalink)  
Old November 4, 2008, 11:18 AM
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Originally Posted by Squeetard View Post
4 simultaneous instructions per core. Straight from the mouth of intel.
http://www.intel.com/pressroom/archi...er_nehalem.pdf

K! I stand corrected. What happeneded to Intel whie I was sleeping LoL
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  #39 (permalink)  
Old November 4, 2008, 11:39 AM
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Quote:
Originally Posted by 1Tanker View Post
Great review guys. Some constructive criticism.

+
- Very thorough testing, research, explanations and conclusions.
- Great photos, gifs, etc.
- Great selection of comparison CPUs.
- 5 runs/bench...OMG! What a workload.
- Great writing style.
_

- Proof-reading. I know... you guys were "under the gun".
Takes out shot gun, starts hunting.. !!

Like people actually do read word for word on everything, images speak the words, and then a little description.. *c'mon where did he run now, reload*
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  #40 (permalink)  
Old November 4, 2008, 11:52 AM
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Quote:
Originally Posted by Tazer-[X] View Post
K! I stand corrected. What happeneded to Intel whie I was sleeping LoL

Hehe. Just look at the performance difference with HT enabled, they did good with this gen. Hardwired reorder buffers also means they don't have to dump stuff in and out if a thread gets preempted.
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